Low fabrication cost, high performance, high reliability chip scale package

ABSTRACT

The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.

BACKGROUND OF THE INVENTION

[0001] (1) Field of the Invention

[0002] The invention relates to the fabrication of integrated circuitdevices, and more particularly, to a method and package forsemiconductor devices.

[0003] (2) Description of the Prior Art

[0004] The creation of semiconductor devices, also referred to asIntegrated Circuits (IC) has been made possible by the rapid developmentof supporting technologies such as photolithography and methods ofetching. Most of these technologies have over the years had to addressconcerns created by a continued decrease in device dimensions andincrease in device densities. This effort of creating improvedperformance devices does is not limited in its impact on the deviceitself but extends into the methods and packages that are used tofurther interconnect semiconductor devices and to protect these devicesfrom environmental damage. This latter issue has created a packagingtechnology that is also driven by continuing demands of deviceminiaturization and denser packaging of devices, this at no penalty todevice performance and in a cost-effective manner.

[0005] Semiconductor device packaging typically mounts a device on asubstrate, such as semiconductor substrates, printed circuit boards,flex circuits, metallized substrates, glass substrates and semiconductordevice mounting support. Such a substrate can be a relative complexstructure, having multiple payers of interconnect metal distributedthroughout the height of the substrate in addition to havinginterconnect traces created on one or both surfaces of the substrate. Inaddition, in order to enable the mounting of semiconductor over thesurface of the substrate, contact pads such as bond pads are typicallyprovided over at least one of the surfaces of a substrate. For morecomplex packages, several levels of packaging may be applied whereby asemiconductor device is mounted on a substrate and connected tointerconnect metal that is part of the substrate, the first levelsubstrate may be further mounted over the surface of a larger substratefrom which the device is interconnected to surrounding circuitry orelectrical components. Limitations that are imposed on this method ofpackaging are typically limitations of electrical performance that isimposed on the device by the packaging interface. For instance, of keyconcerns are RC delays in the transmission of signals over the variousinterconnect traces. This places a restraint of size and thereforepackaging density on the package. Also of concern are considerations ofparasitic capacitance and inductance that are introduced by the packagesince these parameters have a negative impact on device performance, amore serious impact on high frequency device performance. Theseparasitic components must therefore be minimized or suppressed to themaximum extent possible.

[0006] One or the more conventional methods of connecting asemiconductor device to surrounding points of interconnect is the use ofa solder bump. Typically a semiconductor device will be provided on theactive surface of the device with points of electrical interconnectwhich electrically access the device. To connect these points ofinterconnect to for instance a printer circuit board, solder bumps areprovided on the surface of the circuit board that align with the pointsof electrical contact of the device. The creation of this interface isalso subject to requirements imposed by electrical performance of thecompleted package, by requirements of package miniaturization,reliability, cost performance and the like. The invention provides apackage that addresses these packaging concerns in addition to others.

[0007] U.S. Pat. No. 6,181,569 (Charkravorty) shows a solder bumpprocess and structure that includes trace formation and bump plating.

[0008] U.S. Pat. No. 6,107,180 (Munroe et al.) shows a bump processusing UBM and solder bumps.

[0009] U.S. Pat. No. 5,879,964 (Paik et al.) shows a related bump andinterconnect process.

SUMMARY OF THE INVENTION

[0010] A principle objective of the invention is to provide ahigh-pillar solder bump that sustains a high stand-off of the completesolder bump while maintaining high bump reliability and minimizingdamage caused by mismatching of thermal stress factors between theinterfacing surfaces.

[0011] Another objective of the invention is to provide a method thatfurther improves bump reliability by reducing mechanical and thermalstress.

[0012] Yet another objective of the invention is to providere-distribution bumps which enable the creation of a flip-chip packagewithout requiring a change in the design of the Integrated Circuit andwithout modifying the pad pitch, the performance of the package isimproved and the package size does not need to be modified.

[0013] A still further objective of the invention is to provide a chipscale package using one UBM layer of metal, significantly reducing costsof fabrication and materials.

[0014] A still further objective of the invention is to provide a chipscale package whereby the solder ball is removed from the semiconductordevice, eliminating the need for low-alpha solder, thus reducingfabrication cost and concerns of soft-error occurrence.

[0015] In accordance with the objectives of the invention a new methodand chip scale package is provided. The inventions starts with asubstrate over which a contact point is provided, the contact point andthe surface of the substrate are protected by a layer of passivation,the contact point is exposed through an opening created in the layer ofpassivation. A layer of polymer or elastomer is deposited over the layerof passivation, an opening is created through the layer of polymer orelastomer that aligns with the contact point (contact pad), exposing thecontact pad. A barrier/seed layer is deposited over the surface of thelayer of polymer or elastomer, including the inside surfaces of theopening created through the layer of polymer or elastomer and theexposed surface of the contact pad. A first photoresist mask is createdover the surface of the barrier/seed layer, the first photoresist maskexposes the barrier/seed layer where this layer overlies the contact padand, contiguous therewith, over a surface area that is adjacent to thecontact pad and emanating in one direction from the contact pad. Theexposed surface of the barrier/seed layer is electroplated for thecreation of interconnect traces. The first photoresist mask is removedfrom the surface of the barrier/seed layer, a second photoresist mask iscreated exposing the surface area of the barrier/seed layer that isadjacent to the contact pad and emanating in one direction from thecontact pad. The second photoresist mask defines that solder bump. Thesolder bump is created in accordance with the second photoresist mask,the second photoresist mask is removed from the surface of thebarrier/seed layer, exposing the electroplating and the barrier/seedlayer with the metal plating overlying the barrier/seed layer. Theexposed barrier/seed layer is etched in accordance with the patternformed by the electroplating, reflow of the solder bump is optionallyperformed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016]FIG. 1 shows a cross section of a conventional mini-BGA package.

[0017]FIG. 2 shows a cross section of a conventional re-routing bump.

[0018]FIGS. 3 through 8 detail the process flow of the invention, asfollows:

[0019]FIG. 3 shows a cross section of a silicon substrate, a top metalcontact pad has been provided, a layer of passivation and a layer ofpolymer or elastomer have been deposited and patterned over the surfaceof the BGA substrate.

[0020]FIG. 4 shows a cross section after a barrier/seed layer has beendeposited.

[0021]FIG. 5 shows a cross section after a first photoresist mask hasbeen created over the surface of the barrier/seed layer, electroplatinghas been applied for the deposition of metal for the formation ofinterconnect traces.

[0022]FIG. 6 shows a cross section after the first photoresist mask hasbeen removed from the surface of the barrier/seed layer.

[0023]FIG. 7 shows a cross section after a second photoresist mask hasbeen created over the surface of the barrier/seed layer, including thesurface of the electroplated interconnect metal; the second photoresistmask defines the solder bump.

[0024]FIG. 8 shows a cross section after the solder bump has beenelectroplated in accordance with the second photoresist mask.

[0025]FIG. 9 shows a cross section after removal of the secondphotoresist mask, exposing the surface of the barrier/seed layer and theelectroplated interconnect metal.

[0026]FIG. 10 shows a cross section after the barrier/seed layer hasbeen etched in accordance with the layer of interconnect metal.

[0027]FIG. 11 shows a cross section of the package of the invention witha molding compound as encapsulant.

[0028]FIG. 12 shows a cross section of the package of the invention withunderfill as encapsulant.

[0029]FIG. 13 shows a cross section of the package of the inventionusing both molding and an underfill.

[0030]FIG. 14 shows a cross section of the package of the invention as abare die that can be directly attached to a next level substrate.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] Two prior art applications are shown in the cross sections ofFIGS. 1 and 2, specifically in the cross section of FIG. 1 are shown:

[0032]11, a BGA substrate such as a printed circuit board and the like

[0033]12, a semiconductor device or die

[0034]14, a molding compound that is used to encapsulate the die 12

[0035]16, solder balls that form the electrical interface between thepackage shown in cross section in FIG. 1 and surrounding circuitry;these solder balls can for instance be further connected to contact padson the surface of a Printed Circuit Board (PCB)

[0036]18, bond wires used to connect points of electrical contact (notshown) on the active surface of die 12 with contact pads (not shown) onthe second or upper surface of BGA substrate 11.

[0037]FIG. 2 shows a cross section of a conventional re-routing bump,the re-routing applies since the solder bump that is shown in crosssection in FIG. 2 does not align with the contact pad with which thesolder bump is connected. The elements that are highlighted in the crosssection of FIG. 2 are the following:

[0038]10, a device supporting silicon substrate.

[0039]20, a solder ball

[0040]22, top metal contact point

[0041]24, a layer of passivation, applied for the protection of theunderlying surface and the surface of the layer 22 of top metal

[0042]26, a layer of dielectric material

[0043]28, a layer of passivation, applied for the protection of theunderlying layer 26 of dielectric and the surface of the layer 32 ofre-routing metal

[0044]30, a seed and/or barrier layer

[0045]32, a patterned layer of re-routing metal

[0046]33, a seed layer, and

[0047]34, a layer of UBM metal.

[0048]FIGS. 3 through 9 will now be used to describe the invention.Referring specifically to the cross section that is shown in FIG. 3,there is shown:

[0049]10, a semiconductor supporting surface such as the surface of asilicon substrate

[0050]40, a contact pad or top metal pad that has been provided in or onthe surface of the substrate layer 10

[0051]42, a layer of passivation deposited over the surface of layer 10;the layer 42 of passivation has been patterned and etched, creating onopening 41 through the layer 42 of passivation that aligns with thecontact pad 40

[0052]44, a layer of polymer or elastomer that has been deposited overthe surface of the layer 42 of passivation; the layer 44 of polymer orelastomer has been patterned and etched, creating on opening 41 throughthe layer 42 of polymer or elastomer that aligns with the contact pad40. Contact pad 40 can comprise aluminum or copper or a compoundthereof.

[0053] As materials that can be used as a polymer for the deposition oflayer 44 can be cited polyimide, parylene or teflon, electron resist,solid organics or inorganics, BCB (bisbenzocyclobutene), PMMA(poly-methyl-methacrylate), teflon which is a polymer made from PTFE(polytetrafluoroethylene), also polycarbonate (PC), polysterene (PS),polyoxide (PO) and poly polooxide (PPO).

[0054] The semiconductor supporting surface 10 can be semiconductorsubstrates, printed circuit boards, flex circuits, metallizedsubstrates, glass substrates and semiconductor device mounting support,whereby the semiconductor substrate can selected from the group ofsubstrates consisting of semiconductor substrates, ceramic substrates,glass substrates, gallium arsenide substrates, silicon on insulator(SOI) substrates and silicon on sapphire (SOS) substrates.

[0055]FIG. 4 shows a cross section of the semiconductor substrate aftera layer 46 of barrier/seed material has been deposited over t he surfaceof layer 44 of polymer or elastomer; inside surface of opening 41 havealso been covered with the layer 46 of barrier/seed material.

[0056] A typical barrier layer 46 is deposited using rf. sputtering oftitanium nitride, tantalum, tungsten, niobium, molybdenum, Ti/TiN orTi/W and is more preferably formed from TiN. The barrier layer 46 canalso be used to improve the adhesion of a subsequent overlying metallayers. A barrier layer is preferably about 100 and 1000 angstrom thick.

[0057] To further enhance the adhesion of a copper interconnect line tothe surrounding layer of dielectric or insulation, a seed layer isdeposited over the barrier layer. A seed layer can be deposited using asputter chamber or an Ion Metal Plasma (IMP) chamber at a temperature ofbetween about 0 and 300 degrees C. and a pressure of between about 1 and100 mTorr, using copper or a copper alloy as the source at a flow rateof between about 10 and 400 sccm and using argon as an ambient gas. Theminimum thickness of a seed layer is about 5,000 Angstrom, thisthickness is required achieve a reliable gap fill.

[0058]FIG. 5 shows a cross section after:

[0059]48, a first photoresist mask has been formed over the surface ofbarrier/seed layer 46, exposing the surface of the barrier/seed layer46, and

[0060]50, a layer 50 of metal has been over the exposed surface of thebarrier/seed layer 46 in accordance with the opening 43 created in thefirst photoresist mask.

[0061] The process of deposition and patterning a layer of photoresistuses conventional methods of photolithography and masking. Layer 48 ofphotoresist can be etched by applying O₂ plasma and then wet strippingby using H₂SO₄, H₂O₂ and NH₄OH solution. Sulfuric acid (H₂SO₄) andmixtures of H₂SO₄ with other oxidizing agents such as hydrogen peroxide(H₂O₂) are widely used in stripping photoresist after the photoresisthas been stripped by other means. Wafers to be stripped can be immersedin the mixture at a temperature between about 100 degrees C. and about150 degrees C. for 5 to 10 minutes and then subjected to a thoroughcleaning with deionized water and dried by dry nitrogen. Inorganicresist strippers, such as the sulfuric acid mixtures, are very effectivein the residual free removal of highly postbaked resist. They are moreeffective than organic strippers and the longer the immersion time, thecleaner and more residue free wafer surface can be obtained. The opening43 that is in this manner created in the layer 48 of photoresist exposesthe surface of the layer 44 of barrier/seed material over a surface areawhere re-routing metal has to be created.

[0062] Removal of the first photoresist mask 48 from the surface of thebarrier/seed layer 46 results in the cross section that is shown in FIG.6.

[0063] The invention continues with the cross section that is shown inFIG. 7, shown are:

[0064]52, a second photoresist mask is created over the surface of thebarrier/seed layer 46, including the surface of the interconnect metallayer 50, and

[0065]51 opening created in the second layer 52 of photoresist, exposingthe surface of layer 50 of interconnect metal; opening 51 defined thelocation and size (diameter) of the to be created solder bump.

[0066] The cross section that is shown in FIG. 8 is after the opening 51created in the second layer of dielectric has been filled with solderbump material. These materials can be selected as:

[0067] layer 54 being a first layer of metal, typically comprisingcopper, deposited to a thickness between about 10 and 100 μm, and morepreferably to a thickness of about 50 μm

[0068] layer 56 being an UBM layer, typically comprising nickel,deposited to a thickness between about 1 and 10 μm, and more preferablyto a thickness of about 5 μm, forming an integral part of the pedestalof the to be created interconnect bump, and

[0069] layer 58 is a layer of solder compound, deposited to a thicknessbetween about 10 and 100 μm, and more preferably to a thickness of about50 μm.

[0070] With the completion of the electroplating of these three layers,the solder bump is essentially complete. The second solder mask 52, FIG.8, is therefore removed from the surface of the barrier/seed layer 46and the surface of the interconnect metal 50, see FIG. 9, exposing thebarrier/seed layer 46 and the interconnect metal 50, a pattern ofbarrier/seed material overlying the barrier/seed layer 46.

[0071] It is good practice and can be of benefit in the creation of thelayers 54, 56 and 58 of metal to perform, prior to the electroplating ofthese layers of metal, an in-situ sputter clean of the exposed surface(exposed through opening 51) of the layer 50 of re-routing metal.

[0072] The barrier/seed layer 46 can now be etched using the patternedlayer 50 of interconnect metal as a mask, which leads to the crosssection that is shown in FIG. 10.

[0073] It is further good practice to oxidize the surface of the UBM andpillar metal by chemical or thermal oxidation. The chemical oxidationcould be an H₂O₂ oxidation process, at a temperature in excess of about150 degrees C. These processing steps can further help prevent wettingof the solder bump to the metal traces.

[0074] Reflow can optionally be applied the layer 58 of solder compound,creating a spherical layer 58 of solder which forms the solder bump (notshown). It must be noted in the cross section that is shown in FIG. 10that the diameter of the UBM layer 54 is, during and as a consequence ofthe etching of the barrier/seed layer 46, reduced in diameter. Thisallows the solder ball 58 to be removed from the surface of thesubstrate by a relatively large distance. From this follows theadvantage that it is no longer required that low-alpha solder is usedfor the solder compound of solder ball 58, reducing manufacturing costin addition to reducing concerns of memory soft-error conditions.

[0075] Layer 56 of UBM may contain multiple layers of metal such as alayer of chrome, followed by a layer of copper, followed by a layer ofgold. From the latter it is apparent that layer 56 of UBM may compriseseveral layers of metal that are successively deposited.

[0076] Examples of the application of the package of the invention areshown in cross section in FIGS. 11 and 12. Highlighted in FIG. 11 are:

[0077]60, a polymer or elastomer layer provided by the invention,similar to layer 44 of FIG. 3 e.a.

[0078]62, a BGA substrate over which a semiconductcr device is to bemounted

[0079]64, a semiconductor device

[0080]66, a molding compound applied to encapsulate the device 64

[0081]68, contact balls to the package of the invention

[0082]70, pillar metal, similar to layers 54 and 56 of FIG. 8 e.a., and

[0083]72, a solder bump, similar to layer 58 of FIG. 8 after thermalreflow has been applied to this layer.

[0084] Shown in cross section in FIG. 12 is another application of theinvention. The elements that have been applied above under FIG. 11 arevalid for the cross section shown in FIG. 12 with the exception ofelement 74, which in the cross section of FIG. 12 is an underfill thathas been applied under semiconductor device 64 and that replaces layer66 of molding compound in FIG. 11 as the means for encapsulating thedevice 64.

[0085]FIGS. 13 and 14 show additional applications of the invention withFIG. 13 showing a cross section of the package of the invention usingboth molding and an underfill while FIG. 14 shows a cross section of thepackage of the invention as a bare die that can be directly attached toa next level substrate. All elements of the cross sections that areshown in FIGS. 13 and 14 have previously been described and needtherefore not been further highlighted at this time.

[0086] In order to better highlight the differences between the priorart solder bump, as shown in cross section in FIG. 2, and the solderbump of the invention, as shown in the cross section of FIG. 10, theprocessing steps to create these two solder bumps are listed below.These steps are easier to follow if it is realized that both methodsrequire and apply two metal fill plating steps, the first of these twostep is to create a patterned layer of re-routing metal, the second isto create the solder bump. The processing sequences are as follows:

[0087] 1. the prior art starts with a device support substrate, acontact pad has been created over the surface of the substrate, layersof passivation and dielectric have been deposited over the surface ofthe substrate and patterned to expose the contact pad; the inventionstarts with the same structure

[0088] 2. the prior art deposits a first seed layer over the surface ofthe layer of dielectric; the invention does the same

[0089] 3. the prior art performs a first metal fill over the first seedlayer by creating a layer of metal that serves as re-routing metal; theinvention does the same

[0090] 4. the prior art etches the first seed layer; the instantinvention does not perform this step at this time

[0091] 5. the prior art deposits and patterns a layer of passivation,exposing the surface of the layer of re-routing metal, the patternedsecond layer of passivation serves as a mask for the reflow of thesolder bump; the instant invention does not perform this step becausethe solder bump structure will not wet to the re-routing metal

[0092] 6. the prior art deposits a second seed layer over the surface ofthe layer of passivation; the instant invention does not deposit asecond seed layer

[0093] 7. the prior art plates a layer of UBM over which a layer ofsolder compound is plated; the instant invention deposits a layer of UBMand two metal plating steps, the first metal plating step plating alayer of metal, such as copper or nickel that forms an integral part ofthe pedestal of the to be created interconnect bump, the second metalplating step depositing a solder compound

[0094] 8. the prior art performs reflow of the solder compound; theinstant invention does the same

[0095] 9. the prior art etches the second seed layer using the solderball as a mask; the instant invention etches the first seed layer usingthe patterned re-routing metal as a mask.

[0096] The essential differences between the prior art and the instantinvention is provided by the two plating steps and can, for easyreference be summarized as follows: First plating step Prior Art InstantInvention 1^(st) seed layer dep. 1^(st) seed layer dep. plate re-routingmetal plate re-routing metal etch 1^(st) seed layer (no equivalent step)

[0097] Second plating step Prior Art Instant Invention 2^(st) seed layerdep. (no equivalent step) plate UBM + solder plate UBM + metal + solderetch 2^(st) seed layer etch 1^(st) seed layer

[0098] The advantages of the instant invention can be summarized asfollows:

[0099] 1. the height of the metal pillar (layers 54 and 56, FIG. 10)allows for high stand-off between the surface of substrate 10, therebyreducing impact of mismatching of thermal fatigue between interfacingsurfaces such as the surface of the substrate 10 and the layers of metalthat are part of the solder bump

[0100] 2. the layer 44 has been highlighted as being a layer of orpolymer or elastomer and is selected for its ability to provide stressrelease between overlying surfaces and thus to enhance solder bumpreliability

[0101] 3. the re-distribution solder bump of the invention allows forcreating a flip-chip package without the need for semiconductor deviceredesign or changes in the pitch of the contact points of the package(the pitch of contact balls 72 and 68, FIGS. 11 and 12); the packagesize can also remain constant while still being able to package die ofdifferent dimensions (due to the flexibility of the routing of there-routing metal layer 50, FIG. 50, FIG. 10)

[0102] 4. the method of creating the solder pillar and the solder bump,that is plating a layer of UBM over which metal is plated twice,contributes a significant cost saving in both materials used and in themanufacturing cost; the need for separate UBM plating and etching, forseparate plating and etching the pillar metal and for separate platingand etching the solder compound is reduced to using one photoresist maskthat is applied for all three steps

[0103] 5. by creating a relatively high layer of pillar metal, thesolder ball is removed from the surface of the substrate; from thisfollows that low-alpha solder is no longer required as a solder compoundfor the solder bump, reducing manufacturing costs; from this furtherfollows that soft-error concerns that typically apply to memory chipdesigns are less valid using the solder bump of the invention

[0104] 6. by creating a relatively high layer of pillar metal, thesolder ball of the instant invention will not wet to the re-routingmetal trace. Thus, the second layer of passivation material, whichtypically serves as a solder mask, is no longer required and,consequently, processing cost is reduced.

[0105] In sum: the invention provides a method to create a solder bumphaving a high metal pillar and a solder ball. Seed/barrier layerdeposition is limited to one deposition, a first metal plating stepdefines the re-routing metal, a second metal plating step creates thesolder bump. The need for additional layers of passivation or soldermask has been removed.

[0106] Although the invention has been described and illustrated withreference to specific illustrative embodiments thereof, it is notintended that the invention be limited to those illustrativeembodiments. Those skilled in the art will recognize that variations andmodifications can be made without departing from the spirit of theinvention. It is therefore intended to include within the invention allsuch variations and modifications which fall within the scope of theappended claims and equivalents thereof.

What is claimed is:
 1. A method for forming a re-routed metal bump on asemiconductor surface, comprising the steps of: providing asemiconductor surface, at least one contact pad having been provided inor over said semiconductor surface, the surface of said at least onecontact pad being exposed by at least one opening created through alayer of passivation deposited over the semiconductor surface andthrough a layer of dielectric deposited over said layer of passivation;depositing a layer of conductive material over the surface of said layerof dielectric; performing a first plating over the surface of said layerof conductive material aligned with said at least one contact pad,creating a layer of re-routing metal; performing a second plating overthe surface of said layer of re-routing metal, creating a solder bumpcomprising pillar metal having a diameter and a solder compound over thesurface of said re-routing metal; and etching said layer of conductivematerial, using said layer of re-routing metal as a mask, simultaneouslyreducing the diameter of said pillar metal by a measurable amount. 2.The method of claim 1, said layer of conductive material comprising amaterial selected from the group of materials consisting of barrierlayer material and seed layer material.
 3. The method of claim 1, saidperforming a first plating over the surface of said layer of conductivematerial comprising the steps of: forming a first metal deposition maskover the surface of said layer of conductive material, said first metaldeposition mask exposing the surface of said layer of conductivematerial over a surface area that aligns with said at least one contactpad and, contiguous therewith, over a surface area that is adjacent tosaid at least one contact pad and emanating in one direction from saidat least one contact pad; first electroplating a first layer of metalover the surface of said layer of conductive material in accordance withsaid first metal deposition mask, said first electroplating creating alayer of re-routing metal over the surface of said layer of conductivematerial; and removing said first metal deposition mask from the surfaceof said layer of conductive material.
 4. The method of claim 3, saidfirst metal deposition mask comprising photoresist.
 5. The method ofclaim 1, said performing a second plating over the surface of said layerof re-routing metal comprising the steps of: forming a second metaldeposition mask over the surface of said layer of re-routing metal, saidsecond metal deposition mask exposing the surface of said re-routingmetal over said surface area of said re-routing metal that is adjacentto said at least one contact pad and emanating in one direction fromsaid at least one contact pad; second electroplating a second layer ofmetal over the surface of said layer of re-routing metal in accordancewith said second metal deposition mask, said second electroplatingcreating a layer of pillar metal over the surface of said re-routingmetal after which a layer of solder compound is electroplated over thesurface of said pillar metal; and removing said second metal depositionmask from the surface of said re-routing metal, exposing the surface ofsaid layer of conductive material and said re-routing metal.
 6. Themethod of claim 5, said second metal deposition mask comprisingphotoresist.
 7. The method of claim 5, said pillar metal comprising afirst layer of metal created over the surface of said re-routing metaland a second layer of UBM electroplated over the surface of said firstlayer of metal.
 8. The method of claim 7, said layer of UBM comprisingnickel applied to a thickness of between about 1 and 10 μm.
 9. Themethod of claim 7, said first layer of metal comprising copper appliedto a thickness of between about 10 and 100 μm.
 10. The method of claim7, said layer of Under Bump Metallurgy comprising a plurality ofsub-layers of different metallic composition.
 11. The method of claim 5,said layer of solder compound comprising solder applied to a thicknessof between about 30 and 100 μm.
 12. The method of claim 1, saidsemiconductor surface being selected from the group of surfacesconsisting of semiconductor substrates, printed circuit boards, flexcircuits, metallized substrates, glass substrates and semiconductordevice mounting support.
 13. The method of claim 12, said semiconductorsubstrate being selected from the group of substrates consisting ofsemiconductor substrates, ceramic substrates, glass substrates, galliumarsenide substrates, silicon on insulator (SOI) substrates and siliconon sapphire (SOS) substrates.
 14. The method of claim 1, said at leastone contact pad comprising aluminum or copper or a compound thereof. 15.The method of claim 1, further comprising performing an in-situ sputterclean of the exposed surface of said layer of conductive material, saidadditional step being performed prior to said performing a secondplating over the surface of said layer of re-routing metal.
 16. Themethod of claim 1, said layer of dielectric being selected from thegroup of materials consisting of polymer and elastomer.
 17. A method forforming a metal bump on a semiconductor surface, comprising the stepsof: providing a semiconductor surface, at least one contact pad havingbeen provided in or over the surface of said semiconductor surface, alayer of passivation having been deposited over said semiconductorsurface, a layer of dielectric having been deposited over the surface ofsaid layer of dielectric, said layers of dielectric and passivationhaving been patterned and etched creating at least one opening throughsaid layers of dielectric and passivation, said at least one openingthrough said layers of dielectric and passivation being aligned withsaid at least one contact pad, exposing the surface of said at least onecontact pad; depositing a layer of conductive material over the surfaceof said layer of dielectric, including the exposed surface of said atleast one contact pad, said layer of conductive material comprising amaterial selected from the group consisting of barrier layer materialand seed layer material; forming a first metal deposition mask over thesurface of said layer of conductive material, said first metaldeposition mask exposing the surface of said layer of conductivematerial over a surface area that aligns with said at least one contactpad and, contiguous therewith, over a surface area that is adjacent tosaid at least one contact pad and emanating in one direction from saidat least one contact pad; first electroplating a first layer of metalover the surface of said layer of conductive material in accordance withsaid first metal deposition mask, said first electroplating creating alayer of re-routing metal over the surface of said layer of conductivematerial; removing said first metal deposition mask from the surface ofsaid layer of conductive material; forming a second metal depositionmask over the surface of said layer of re-routing metal, said secondmetal deposition mask exposing the surface of said layer of re-routingmetal over said surface area of said layer of re-routing metal that isadjacent to said at least one contact pad and emanating in one directionfrom said at least one contact pad; second electroplating a second layerof metal over the surface of said layer of re-routing metal inaccordance with said second metal deposition mask, said secondelectroplating creating a layer of pillar metal over the surface of saidre-routing metal after which a layer of solder compound is electroplatedover the surface of said pillar metal; removing said second metaldeposition mask from the surface of said layer of re-routing metal,exposing the surface of said layer of conductive material and saidre-routing metal; and etching the exposed surface of said layer ofconductive material using said layer of re-routing metal as a mask,simultaneously reducing a diameter of said second electroplated pillarmetal by a measurable amount.
 18. The method of claim 17, said firstmetal deposition mask comprising photoresist.
 19. The method of claim17, said second metal deposition mask comprising photoresist.
 20. Themethod of claim 17, said pillar metal comprising a first layer of metalcreated over the surface of said re-routing metal and a second layer ofUBM electroplated over the surface of said first layer of metal.
 21. Themethod of claim 20, said layer of UBM comprising nickel applied to athickness of between about 1 and 10 μm.
 22. The method of claim 20, saidsecond layer of metal comprising copper applied to a thickness ofbetween about 10 and 100 μm.
 23. The method of claim 20, said layer ofUnder Bump Metallurgy comprising a plurality of sub-layers of differentmetallic composition.
 24. The method of claim 17, said layer of soldercompound comprising solder applied to a thickness of between about 30and 100 μm.
 25. The method of claim 17, said semiconductor surface beingselected from the group of surfaces consisting of semiconductorsubstrates, printed circuit boards, flex circuits, metallizedsubstrates, glass substrates and semiconductor device mounting support.26. The method of claim 25, said semiconductor substrate being selectedfrom the group of substrates consisting of semiconductor substrates,ceramic substrates, glass substrates, gallium arsenide substrates,silicon on insulator (SOI) substrates and silicon on sapphire (SOS)substrates.
 27. The method of claim 17, said at least one contact padcomprising aluminum or copper or a compound thereof.
 28. The method ofclaim 17, further comprising performing an in-situ sputter clean of theexposed surface of said layer of re-routing metal, said additional stepbeing performed prior to said second electroplating a second layer ofmetal over the surface of said layer or re-routing metal.
 29. The methodof claim 17, said layer of dielectric being selected from the group ofmaterial consisting of polymer and elastomer.
 30. A Chip Scale packageusing re-routed bump metal on a semiconductor surface, comprising: asemiconductor surface, at least one contact pad having been provided inor over said semiconductor surface, the surface of said at least onecontact pad being exposed by at least one opening created through alayer of passivation deposited over the semiconductor surface andthrough a layer of dielectric deposited over said layer of passivation;a layer of conductive material deposited over the surface of said layerof dielectric; a first plating provided over the surface of said layerof conductive material aligned with said at least one contact pad,creating a layer of re-routing metal; a second plating provided over thesurface of said layer of re-routing metal, creating a solder bumpcomprising pillar metal having a diameter and a solder compound over thesurface of said re-routing metal; and said layer of conductive materialhaving been etched, using said layer of re-routing metal as a mask,having simultaneously reduced the diameter of said pillar metal by ameasurable amount.
 31. The Chip Scale package of claim 30, said layer ofconductive material comprising a material selected from the group ofmaterials consisting of barrier layer material and seed layer material.32. The Chip Scale package of claim 30, said pillar metal comprising afirst layer of metal Under Bump Metallurgy (UBM) created over thesurface of said re-routing metal and a second layer of Under BumpMetallurgy (UBM) electroplated over the surface of said first layer ofmetal.
 33. The Chip Scale package of claim 32, said layer of UBMcomprising nickel applied to a thickness of between about 1 and 10 μm.34. The Chip Scale package of claim 32, said second layer of metalcomprising copper applied to a thickness of between about 10 and 100 μm.35. The Chip Scale package of claim 32, said layer of Under BumpMetallurgy comprising a plurality of sub-layers of different metalliccomposition.
 36. The Chip Scale package of claim 30, said layer ofsolder compound comprising solder applied to a thickness of betweenabout 30 and 100 μm.
 37. The Chip Scale package of claim 30, saidsemiconductor surface being selected from the group of surfacesconsisting of semiconductor substrates, printed circuit boards, flexcircuits, metallized substrates, glass substrates and semiconductordevice mounting support.
 38. The Chip Scale package of claim 37, saidsemiconductor substrate being selected from the group of substratesconsisting of semiconductor substrates, ceramic substrates, glasssubstrates, gallium arsenide substrates, silicon on insulator (SOI)substrates and silicon on sapphire (SOS) substrates.
 39. The Chip Scalepackage of claim 30, said at least one contact pad comprising aluminumor copper or a compound thereof.
 40. The Chip Scale package of claim 30,said layer of dielectric being selected from the group of materialsconsisting of polymer and elastomer.
 41. The method of claim 1, thesurface of said pillar metal being oxidized by applying chemical orthermal oxidation.
 42. The method of claim 17, the surface of saidpillar metal being oxidized by applying chemical or thermal oxidation.43. The method of claim 17, with an additional step of applying a stepof reflow to said layer of solder compound.
 43. The method of claim 7,the surface of the UBM and pillar metal additionally being oxidized bychemical or thermal oxidation.
 44. The method of claim 43, saidadditionally oxidizing being an H₂O₂ oxidation process, at a temperaturein excess of about 150 degrees C.
 45. The method of claim 20, thesurface of the UBM and pillar metal additionally being oxidized bychemical or thermal oxidation.
 46. The method of claim 45, saidadditionally oxidizing being an H₂O₂ oxidation process, at a temperaturein excess of about 150 degrees C.